LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY shift_8x64_taps IS
PORT (
	clk : 			IN STD_LOGIC;
	shift : 			IN STD_LOGIC;
	sr_in : 			IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	sr_tap_one : 			OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	sr_tap_two : 			OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	sr_tap_three : 			OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	sr_out : 			OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END shift_8x64_taps;

ARCHITECTURE arch OF shift_8x64_taps IS

SUBTYPE sr_width IS STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE sr_length IS ARRAY (63 DOWNTO 0) OF sr_width;

SIGNAL sr : sr_length;

BEGIN
	PROCESS (clk)
	BEGIN
		IF (clk'EVENT and clk = '1') THEN
			IF (shift = '1') THEN 
				sr(63 DOWNTO 1) <= sr(62 DOWNTO 0);
				sr(0) <= sr_in;
			END IF;
		END IF;
	END PROCESS;

	sr_tap_one <= sr(15);
	sr_tap_two <= sr(31);
	sr_tap_three <= sr(47);
	sr_out <= sr(63);

END arch;
